The technical structure of an LCD TV is mainly divided into two parts: the backlight system and the image display system. The backlight driver section primarily adopts CCFL or LED lighting technology. The image display section converts network signals or video interface signals (such as analog signal interfaces or digital interface such as HDMI) into digital image signals, which are then transmitted to the screen driver chip via the LVDS interface. For larger-sized and higher-end TVs, which need to support higher resolutions and other advanced functions, the V-by-One interface is commonly used for signal transmission.

This solution is applicable to LCD TVs, especially larger-sized, higher-end LCD TVs that need to support higher resolution, as well as LCD TV display systems that require dynamic timing reconstruction, intelligent image processing and interface bridge conversion functions.

Features

• Timing Reconstruction & Intelligent Image Processing:

  Based on the flexible programmability, parallel processing and flexible programming clock tree of FPGA, it can realize dynamic timing reconstruction and intelligent image processing, such as 3D-LUT color calibration, dynamic backlight control algorithm, bad pixel compensation, etc., and is widely used.

• Interface Bridge Conversion:

  Due to the compatibility of various interfaces, FPGA can also perform HDMI to LVDS and DP to LVDS bridging conversion functions.

LCD TV Display System

The LCD TV display system usually requires image signals to be transmitted to the TCON via Mini LVDS, transmits image data to the Column Driver. While the Row Driver controls the system scanning through an independent timing signal, used for drive control to achieve image driving and display.

Functional Units in Logic Board

1. Power Management Unit (PMU):

   Converts a 12V input into multiple voltage rails required by the FPGA, GAMA IC, and LCD panel. Voltage debugging and configuration are performed by a microcontroller cooperating with PC applications through the I2C interface.

2. Main Control Unit:

   Core devices include an FPGA, SPI Flash, and encryption IC.

3. GAMA Voltage Generation Unit:

   Uses a dedicated configurable GAMA IC to generate 12 to 16 channels of GAMA voltages for the panel. It also supports online debugging via the I²C interface.

TCON Board Signal Interfaces

TCONs are mainly driven by LVDS and V-by-One signals, depending on the signal resolution.

• The V-by-One protocol:

  A signal transmission interface standard for flat panel displays developed by THine Electronics, Japan. It employs SERDES technologies such as clock signal recovery, achieving a maximum transmission rate of 3.75 Gbps per differential pair. Anlogic’s PH1A, PH2A, and PH1P series FPGAs support multi-lane high-speed SERDES and are compatible with V-by-One interfaces. Most mainstream 4K TV mainboards adopt the V-by-One interface, which can be implemented for transmit and receive operations using the PH1A90 or PH1A180 devices.

• LVDS display interfaces:

  There are two standards for LVDS display interfaces transmitting video signals: the JEIDA standard and the VESA standard, differing in RGB channel ordering. The LVDS standard defines 4 data lanes and 1 clock lane per group, with a 74.25 MHz clock that transmits 7 bits per clock cycle, resulting in a data rate of 519.75 Mbps. FPGAs readily support transmission and reception at this rate.

• USI-T protocol:

  The USI-T protocol is a panel-driving standard proposed by Samsung for televisions. It is widely adopted in current 4K TV panels, where each signal pair is independent and carries clock signals, video parameters, GAMA parameters, pixel data, and other information, with speeds ranging from 600 Mbps to 1.6 Gbps.

FPGA Applications in TCON Display Solutions

The EG4 series and PH1A90 series FPGAs provide comprehensive support for TV display systems, enabling seamless video reception, high-speed data transmission, and intelligent panel control. They are mass-deployed in TV products to deliver superior display performance.

Features

• Mini-LVDS Protocol Support:

  Typically consists of 1 clock lane and 6 data lanes per group, with clock frequencies adjusted from 148.5 MHz to 297 MHz based on data throughput. It transmits 2 bits per clock cycle, corresponding to a data rate of 297 Mbps to 594 Mbps.

• 4K & Higher-Resolution Display Solution:

  Implemented on the EG4 series, supports video reception and panel driving for high-definition applications.

• Intelligent Display & Dimming Control:

  FPGAs or V-by-One ASIC chips, often paired with GPU video processors, drive higher-resolution image signals and enable high-zone local dimming control.

• Mass Production Deployment:

  The PH1A90 series FPGAs, leveraging the flexible high speed interface and rich logic resource, with customer VBO expertise, are widely adopted in mass-produced TV customers’ designs to achieve intelligent display and dimming control of the panel.