Anlogic provides LED display driver systems based on its FPGAs, with PH1P35 and PH1P50 series as core devices, to meet the demand for efficient LED display driving. This solution is applicable to scenarios that require single-card large-area driving, diversified video data processing, efficient communication protocol operation and image data processing, which can be matched with Anlogic PH1P35 and PH1P50 series.

Features

• Gigabit Transmission & Large-Area Driving:

  Based on Anlogic FPGAs, supports Gigabit Ethernet/high-speed data transmission and single-card large-area driving.

• Abundant Logical Resources:

  Rich on-chip logic for diversified video processing and dot-matrix driving.

• Integrated Hardware (PH1P35 & PH1P50):

  Built-in MCU hard core and DDR memory.

• Efficient Data Processing:

  Simplifies communication protocols and improves correction data efficiency.

• Flexible Resource Utilization:

  Frees FPGA logic for more driving and image processing functions.

  
  

Advantages of FPGA Technical Architecture

• Rich FPGA I/O voltage standards support the construction of high-speed network transmission link systems such as 1Gbps and 5Gbps.

• MCU can implements protocol and data parsing/processing, correction data management, and other intelligent control. Realize intelligent interaction between MCU and FPGA logic through the bus, it reduces FPGA logic resource consumption and subsequent maintenance time, enabling the system to support more display functions.

• The SERDES in the PH1P50 series meets high-bandwidth requirements, with a single SERDES lane delivering 5–10Gbps data rate. The 4-lane SERDES supports DP/HDMI high-definition speed, providing a cost-effective solution for direct video connection.

• FPGA integrates DDR memory with bandwidth supporting 6.4~8.5GB enables image and correction data buffering. The single-chip solution significantly reduces power consumption, improves memory bandwidth, lowers customers' PCB BOM costs, and shortens development cycles.

• The FPGA Dual Boot scheme enhances receiving card functionality, supporting high-definition image data driving for both constant-current sources and PWM drivers.

• 16–20bit grayscale control precision, supporting ultra-high refresh rates above 3840Hz (flicker-free when captured by mobile phones).

• Dynamic programmable gamma correction.

• Linkage with the LED automatic calibration system for automatic compensation of LED attenuation curves.

• Leveraging FPGA’s programmable logic resources, The increase and expansion of both display effects and driver chips of LED screens can achieve unlimited functional reconfiguration and iteration.

• Zero-latency response: The system achieves synchronous display across multiple cards from video signal input at the FPGA to LED output.

• Fault self-healing: Cyclic detection of dead pixels on the screen.

PH1P FPGA LED Solution

Features

• Highly Integrated Architecture:

  Built-in large on-chip image cache and high-speed interface MCU, deeply integrating FPGA programmability with LED processing.

• Precise & Flexible Control:

  Pixel-level precise control, suitable for high-end LED scenarios such as high-density small-pitch, conference all-in-one, cinema screens).

• Cost-Effective & Low Power:

  Reduces BOM, development costs and power consumption.

• Intelligent Pixel Art:

  Turns each LED unit into an intelligent pixel for artistic expression.